1. Field of the Invention
The present invention relates to a method and apparatus for flattening sintered multilayer ceramic electronic substrates used in the production of microelectronic chips.
2. Description of Related Art
State-of-the-art flattening in a continuous furnace for alumina single chip module (SCM) multilayer ceramic (MLC) products involve the use of molybdenum boats, typically with five to six layers to carry product. Each boat layer can carry 16 to 36 products depending on how much weight each product must see to obtain an acceptable final flatness. Typically, four to nine reference products would be placed under one flattening weight, and four such weights would be loaded in a given boat layer. A typical flattening process requires heating the samples under a 0.2-0.5 kg weight (about 1000-3000 Pa) to over 1400° C. and then maintaining them at high temperature for about one hour to achieve an acceptable process yield, under existing flatness specification levels. Typical heating rates are 2-4° C./min, with a lower rate for cooling. The process operating temperature is selected to exceed the ceramic liquid phase melting point to facilitate flattening. Since the processing conditions during flattening do not involve any throughput-limiting chemical reaction, but need only to keep some moderate control on temperature gradient in the loading boat, usual boat loading frequencies fall in the 20-30 min range, resulting in a total processing time of 16 to 20 hours for a typical continuous furnace.
Typically, post sintering process specifications for flatness require top surface camber or flatness of less than 30 μm in the chip site area to enable reliable and-efficient chip joining process, and less than 75 to 125 μm on the product bottom surface to enable second level interconnect processes, such as ball grid array (BGA), land grid array (LGA) or pins. Since the total boat weight is usually limited by the furnace design characteristics, and the flattening weight per product is set by the level of product rework required, it is generally not possible to maximize the tool throughput arbitrarily. However, for the reference product type and typical rework level requirements, it is possible to expect the tool throughput to be in the 4000 to 8000 samples/day range.
Additional flattening steps are used when one flattening pass is not sufficient to bring the product into the desired flatness range, but the efficiency of the process decreases with every additional processing step mainly due to continuous dissolution of alumina into the ceramic liquid phase during maximum heating temperature, which results in a more refractory liquid phase. Also, with such additional processing steps, the product size continues to decrease due to sintering, increasing the chance that the product falls below size specification range. From a mechanical point of view, the use of a fixed flattening load on a given product is also expected to reduce in effectiveness as the products get flatter since the given load is distributed onto an increasingly larger area. Further, surface contamination problems such as glassy vials and fused ceramic are likely to increase due to interaction between the product and the flattening hardware at the process operating temperature.
The need to maximize furnace throughput to control processing costs drives the practice of loading many products under a given weight during flattening. However, not all products have the same level of out-of-flatness after sintering; consequently not all products see the same level of flattening in a typical processing tool. Thus, state-of-the-art flattening processes are not expected to improve the distribution of flatness on a given product batch, but may sometimes increase the measurement data dispersion while simultaneously reducing the average flatness of a product batch.
Alumina MLC yields, unit cost, and reliability are directly dependent on product dimensional control. But the increasing package design complexity, driven by the increasing chip complexity and performance, has increased significantly the difficulties in maintaining product dimensions below existing specs. Furthermore, design pitch enhancements for future products will increase the challenge to design and manufacturing sectors, particularly driven by the need to reduce the local camber in the chip-site area below 25 μm. The current process to resolve this problem is to flatten the products, but the existing process and tool used to flatten these products are inefficient and somewhat capacity limited.